Silicon photonic architecture for training deep neural networks with direct feedback alignment

There has been growing interest in using photonic processors for performing neural network inference operations; however, these networks are currently trained standard digital electronics. Here, we propose on-chip training of enabled by a CMOS-compatible silicon architecture to harness the potential massively parallel, efficient, and fast data operations. Our scheme employs direct feedback alignment algorithm, which trains error rather than backpropagation, can operate at speeds trillions multiply-accumulate (MAC) operations per second while consuming less one picojoule MAC operation. The exploits parallelized matrix-vector multiplications arrays microring resonators processing multi-channel analog signals along single waveguide buses calculate gradient vector each layer situ. We also experimentally demonstrate deep with MNIST dataset operation results. novel approach ultra-fast showcases photonics as promising platform executing AI applications.